1. Field of the Invention
This invention relates to a semiconductor memory device that performs time-division operation, and more particularly to a decoding peripheral circuit that improves the operating frequency.
2. Description of the Related Art
Semiconductor memory devices speed up the input/output of data using the pipelining scheme. The pipelining scheme is a technique for effecting time-division memory accessing. This technique divides a memory access into two to three pipelining stages and thereby achieves data transfer at a high frequency.
FIG. 1 is a timing chart for the counting up of a conventional address signal using an external clock. This is related to the type that takes in a clock signal from an external circuit and generates an address signal internally. The external clock signal is here called a read enable signal/RE (the reverse of signal RE, a rising signal). In the figure, a 3-bit address signal is shown as an example.
FIG. 2 is a circuit diagram of a column decoding means, centering around the necessary component parts to which the signals of FIG. 1 are applied. A column gate 105 is controlled via a decoder 104 that is operated according to the outputs of address registers 101 to 103 formed within an address buffer. One end of the current path of the column gate 105 is connected to a data register 106 that retains the data in a memory cell and its other end is connected to an input/output terminal I/O of the data.
An explanation will be given with reference to FIGS. 1 and 2. The address signals (A2, A1, A0) held in the address registers 101 to 103 are incremented from (0, 0, 0) to (0, 0, 1). (A2, A1, A0) is the address signal held in the address buffer and (A2d, A1d, A0d) is the address signal received by the decoder.
Namely, when the address signal held in the address registers changes, the decoder 104 receives the address signal at the falling edge of signal/RE. That is, the actual address signal output does not begin until period T2 starts. In period T2, the cell for the address signal (0, 0, 1) is selected and the data in the selected cell is latched in a data register. In period T3, an output buffer (not shown) outputs the data. In this way, by counting up the address signal for one period in advance, the time required to count up the address signal is reduced. This makes it possible to read the memory according to the address signal in a shorter period.
As described above, the address signal is actually outputted to the decoder after period T2 in the read operation has started. Therefore, a delay time of DT from when the address signal left the address buffer (address register) until it reaches the decoder is added to the read cycle. That is, in period T2, a practical memory access operation is carried out in such a manner that after the decoding operation corresponding to the specified address signal, the address for the corresponding memory cell is accessed via the data register 106.
Therefore, period T2 contains a critical path, the most time-consuming part of the memory access operation. In the critical path, circuits containing an analog operation region where a potential is transmitted to a bit line or a data line are operated. Thus, the operating frequency of the memory device is virtually synchronized with period T2. When period T2 contains a delay time of DT, this means that it is very difficult to make operation faster by making the period of clock signal as short as possible.
Furthermore, memory devices provided with redundancy circuits for relieving defective memory cells are available. The redundancy circuit senses that the address signal corresponding to a defective memory cell has been inputted, stops accessing the defective memory cell, and selects a redundancy cell (a spare memory cell) in place of the defective one. If the redundancy circuit was provided in a memory device of the above-described synchronization type, the device would be caused to operate in the pipelining stage of period T2 with a critical path. Since the redundancy circuit contains the operation of judging whether or not the signal is the address signal specifying the defective memory cell, this makes the critical path longer, preventing the maximum operating frequency from being improved.